(1) Field of the Invention
The present invention relates to a semiconductor memory device having, in a cell structure capable of satisfactorily maintaining the capacity, a stacked capacitor with a memory cell whose planar surface area can be made small.
(2) Description of the Related Art
A conventional stacked dynamic random access memory (DRAM) of the kind to which the present Invention relates will first be described below with reference to FIG. 1.
In FIG. 1, the conventional stacked DRAM includes a semiconductor substrate 1; a field oxide film 2; a gate oxide film 3; a gate electrode 4 made of polysilicon; a side-wall 6 which is provided to the gate electrode 4 and which is made of an oxide film; an impurity diffusion layer 7; interlayer insulation layers 8, 14 and 16; a storage electrode contact 9; a first electroconductive film 10 which constitutes one part of a capacity storage electrode; a second electroconductive film 11 which constitutes another part of the capacity storage electrode; a capacity insulation film 12; a capacity opposed electrode 13; a bit line 15 which is made of a high melting-point metal silicide, and contacts impurity diffusion layer 7 to form a bit line contact 23 and an aluminum wiring 17.
An advantage in such a conventional semiconductor memory device as explained above is that, even where a planar surface area of the cell is made in the order of, for example, 10 .mu.m.sup.2 or less, the surface area of the first electroconductive film 10 constituting one part of the capacity storage electrode can be made sufficiently large, thereby allowing a sufficient capacitance to be maintained, so that the holding time of charge for information is made long and the resistance to soft-error due to radiations of such as alpha-ray is made higher.
However, a recent trend in this field is to make semiconductor memory devices further miniaturized in structure. With the progress of this trend, there is a strong demand for a planar surface area of a memory cell to be further reduced. If it is reduced, for example, to about 5 .mu.m.sup.2 or less, it becomes difficult to form the storage electrode contact 9 with a sufficient space (for example, about 0.3 .mu.m or more) being provided from the gate electrode 4 to maintain the electrical insulation between the capacity storage electrode 11 and the gate electrode 4. On the other hand, if the above-mentioned space is made as small as, for example, about 0.2 .mu.m or less in the prior art arrangement, there will be a problem in that the electrical insulation between the gate electrode 4 and the capacity storage electrode 11 can no longer be maintained. This is a problem to be solved by the invention in the conventional semiconductor memory device.